1. Field of Invention
The present invention relates to a single-step debug card and, in particular, to a single-step debug card using the peripheral component interconnect (PCI) interface.
2. Related Art
FIG. 1 depicts a structural block diagram of a computer system commonly used nowadays. Obviously, the CPU 10 connects to a north bridge (NB, a chipset) 30 through a CPU bus 20. Other than connecting to memory 40 (which can be SDRAM, EDORAM, etc), the NB 30 also connects to an AGP VGA card 60 through an AGP bus 50. The NB 30 also connects to a south bridge (SB, also a chipset) 80 through a PCI bus 70 for transferring data and information. Other than connecting with the hard drive (HD) 90, the CD-ROM 100, the universal serial bus (USB) 110, input devices (such as the mouse and keyboard) 120 for retrieving or inputting data, the SB 80 also connects to the basic input/output system (BIOS) 150 and the audio device (such as a sound blaster card) 160 through an XD bus 130 and an ISA bus 140, respectively.
The conventional single step interruption debug card is applied to an industry standard architecture (ISA) bus for terminating the IOCHRDY signal of the ISA bus cycle and forcing it to be at the low voltage. The object is to elongate the bus cycle so as to inspect the related address and the state of the data line bus.
On the PCI bus, the access of the CPU to the conventional BIOS has to first transfer the access cycle from the PCI bus to the ISA bus through a PCI/ISA bridge. After the BIOS data is read out by ROM on the ISA bus, the data are sent from the ISA bus back to the PCI bus through the PCI/ISA bridge. Since the BIOS data access cycle on the PCI bus has to be responded through and by the PCI/ISA bridge, that is, the relevant PCI cycle control signals such as DEVSEL# and TRDY# have to be generated by the PCI/ISA bridge, it is impossible to suspend the bus cycle by simply keeping the signals that terminate the PCI cycle (such as TRDY#) at the high voltage.
The debug cards for the PCI bus available on the market have to rely on the assistance of the ISA bus interruption debug cards so as to force the IOCHRDY signal that terminate the ISA bus cycle to be at the low voltage, thus elongating the lifetime of the bus cycle. Or alternatively, at the beginning of booting the computer, part of the BIOS data and address are latched into buffer memory and are read out later. This does not really suspend the bus cycle to perform the real-time inspection function.